The present invention relates to a method for making a substrate of the “semiconductor on insulator” type comprising an integrated ground plane, this substrate being intended to be used in the making of electronic components.
A substrate of the “semiconductor on insulator” type, also known under the acronym SeOI (Semiconductor On Insulator) comprises a layer of insulating material buried between two semiconducting material layers.
As a reminder, the structure of a field effect transistor will now be described with reference to the appended FIG. 1, which schematically illustrates a substrate on which a transistor has been created.
With reference to this figure, it may be seen that the transistor comprises a substrate W inside which a source S, a drain D and a gate G have been formed. The passing of the current between the source S and the drain D is controlled according to the voltage applied to the gate G. The space extending between the source and the drain is called the channel C.
FIG. 2 schematically illustrates a substrate W′, known under the acronym SOI (Silicon On Insulator), on which a transistor has been formed. The insulator layer I is located immediately under the source S and the drain D, themselves formed in the active silicon upper layer A of the substrate W′.
By using a substrate of the SOI type instead of a substrate in bulk silicon as the one illustrated in FIG. 1, the performances of the electronic components may be improved, in particular for CMOS technologies. By the presence of a buried oxide insulating layer I in the substrate, it was actually possible to:                reduce the multiple parasitic couplings existing between several circuits made on a same substrate W′ and,        improve the performances of CMOS circuits operating at high frequency.        
The increasing reduction in the dimensions of the electronic components, the increase in their integration density and the significant increase in the communication rate between the source and the drain have led to the development of increasingly smaller components, which has also resulted in a reduction of the length of the channel C extending between the source S and the drain D.
Now, the reduction of the dimension of this channel leads to the occurrence of a so-called “short channel effect” phenomenon, known under the acronym of SCE (Short Channel Effect), i.e. upon occurrence of an electrostatic field between the source S and drain D which interferes with the displacement of the electrons between both of these elements.
By using transistors known to one skilled in the art under the acronym of MOS PD (Metal Oxide Silicon Partially Depleted), in which the thickness of the active silicon layer A is larger than the maximum depletion depth in the channel, the performances of standard transistors on SOI may be improved by reducing the dimension of the space charge areas associated with the source and with the drain of the transistor.
By using MOS transistors, made on SOI type substrates with a thin silicon film, also known to one skilled in the art as MOS FD (Metal Oxide Silicon Fully Depleted) transistors, it was possible to further reduce the short channel effects and to obtain good electric characteristics of thin transistor, even at a low operating voltage. These FD transistors are obtained by reducing the thickness of the active silicon layer A to a value less than the width of the depletion area, i.e. the space charge area generated by migration of the minority carriers in the channel C.
With substrates of this type, the risks of current passing between the source S and the drain D of the transistor are very limited, or even suppressed and the variation of the threshold voltage related to the reduction in the length of the channel C is highly reduced. Other short channel effects, such as the modulation of the length of the channel and the reduction of the potential barrier of the channel by the drain known to one skilled in the art under the acronym DIBL (Drain Induced Barrier Lowering) are also less significant in MOS SOI FD devices than in the so-called Partially Depleted (PD) ones.
The dimensional reduction in the size of the components and therefore in the length of the channel induces a lowering of the potential barrier between the source and the drain resulting from the superposition of the space charge areas of the source junctions and of that of the drain. The threshold voltage of the transistor then decreases. This effect is known under the name of <<short channel effect>>. This effect is independent of the source-drain voltage applied to the transistor. It only depends on the length of the gate of the transistor. On the other hand, if the source-drain voltage is increased, the threshold voltage reduction will be amplified due to the short channel effect: the barrier will be further reduced. It is this amplification of the threshold voltage reduction which is called DIBL.
A further way for improving the capabilities of the field effect transistors and especially for significantly reducing the short channel effects consists of making the transistor on an SOI type substrate, the buried oxide layer of which is of a small thickness. Reference may be made on this subject to the article of Fenouillet Beranger; “Requirements for ultra-thin-film devices and new materials on CMOS Roadmap”; IEEE 2003.
Thus, with an SOI type substrate, in which the oxide layer I is of the order of 20 nm and the upper silicon film of 5 nm, the short channel effects may be completely suppressed. Reference may be made on this subject to the article of Furczak et al; “Silicon-on-Nothing (SON)—an Innovative Process for advanced CMOS”, IEEE TED, Vol. 47, No. 11, November 2000.
However, if the thickness of the insulated layer I is strongly reduced, for example by using substrates of the thin buried oxide layer type, known under the acronym of “thin BOX”, or even with an ultra thin oxide layer, known under the acronym “UTBOX” (Ultra Thin Buried Oxide), the electrostatic field extends right into the bulk portion of the substrate located below the insulating layer I, which is detrimental to proper operation of the transistor because this phenomenon causes dispersion of the threshold voltage of the transistor.
A known solution to one skilled in the art for avoiding the leaking of electrons into the bulk portion of the substrate consists of forming a ground plane under the insulating layer of the substrate.
Such an exemplary substrate, referenced as W″, is illustrated in the appended FIG. 3. The ground plane bearing the reference GP is formed under the insulating layer I.
From the article of Gallon et al; “Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster”, IEEE SOI 2006, a method is already known for making a ground plane which consists of doping the bulk portion of the substrate by implantation. In this case, implantation is accomplished over the whole surface of the substrate, in order to create a continuously buried ground plane GP, under the totality of the electronic component. It appears that the thinner is the thickness of the insulating layer I, and more the doping step by implantation with phosphorus for p-MOS type transistors or with boron for n-MOS type transistors is facilitated.
From document U.S. Pat. No. 6,391,752, a method is also known which consists of doping by implantation exclusively the area located under the channel and not the areas located under the source or under the drain of the component.
The method consists of forming a sacrificial layer on an SOI substrate, of forming in said sacrificial layer a window, through which one proceeds with doping, and then of forming the gate in said window.
This method has the disadvantage of being costly because it requires many manufacturing steps (masking, etching, implanting, depositing different layers). Further, the use of ionic implantation of dopants in order to produce the ground plane, is limited by the limiting solubility of the dopants in the silicon layer. This limit imposes a restriction on the conductivity which may be attained and therefore on the efficiency of the ground plane. Finally, the disadvantage of using a ground plane obtained by ionic implantation after forming the components, as described in document U.S. Pat. No. 6,391,752, is that this implantation generates defects in the oxide and in the substrate which will then limit the effect of the ground plane.
Finally, another method consists of forming a metal layer instead of ionic implantation of the dopants. With this solution it is possible to have a ground plane having significant conductivity and therefore more efficient as compared with the implantation of dopants.
The known methods of the prior art have disadvantages and lead to limitations. They require the addition of many costly steps in the line for making the transistor. Further, the ground plane made by dopant implantation after making the transistor will have geometrical and electrical properties limited by the ionic implantation technology (solubility limit of the dopants, limit of the depth-thickness pair of the active layer since the implantation energy parameter involves depth but also imposes that the implantation profile be flared).